Correct Designs has immediate openings for talented Verification Engineers to join our project team in Austin, TX. 

We are currently seeking Senior Engineers with extensive high speed IO (SerDes), and PHY experience for a long term (1-2 year) project in Austin. In this role, you will have the opportunity to join a global team and make significant contributions to groundbreaking IP. (Alternate work location for this role is Raleigh, NC.)

What will you do in this role?

• Perform verification of a high-speed I/O design
• Simulate mixed-signal/asynchronous designs with AMS
• Use Verilog testbenches for mixed-signal designs
• Bridge the gap between small-slice Verilog AMS model and UVM/coverage-driven testbenches
• Work closely with the design team to understand calibration sequence and upper protocol layers

What knowledge and experience should you have?

• 10+ years of Functional Verification is required
• Extensive testbench and automated test case design
• Strong programming skills (C++, Linux OS, VHDL, Verilog)
• NCSIM (Xcelium)
• Experience with high speed digital circuits (SerDes)
• Sim coverage collection and analysis

What else would be helpful?

• Knowledge of base analog designs (impedance/offset calibrations) and interaction with Logic. (e.g., A/D Converters)
• AMS modeling

What educational background should you have?

• BS Degree or higher in EE, CS, or CE

Applicants must be legally authorized to work in the U.S. without current or future sponsorship.

About Correct Designs
Correct Designs is a team of Design and Verification experts. Since 1999, Correct Designs has provided world class verification consulting and training services to top semiconductor clients nationwide.

In addition to offering our engineers the opportunity to participate in challenging projects with industry-leading teams, we offer unequaled in-house training in advanced verification tools and methodologies. With CDI, you’ll have the opportunity to enhance your skills in areas such as UVM, SystemVerilog, in-depth SystemVerilog Assertions, and Verification Planning.

Follow us on LinkedIn: https://www.linkedin.com/company/152008/