Current Openings >> SOC Design Verification Engineer
SOC Design Verification Engineer
Summary
Title:SOC Design Verification Engineer
ID:1029
Location:Austin
Description

Correct Designs has immediate openings for talented Verification Engineers to join our senior project team in Austin, TX. We are currently seeking Senior Verification Engineers with experience  for a long term (1+ year) project in Austin. In this role, you will have the opportunity to join a global team and make significant contributions to groundbreaking IP.


What will you do in this role?

As a Correct Designs Senior Consulting Engineer, you will perform ASIC verification at IP and possibly Top Level in a SystemVerilog/UVM/C environment.  You will be responsible for block verification of communication ASIC products - mainly for signal processing.   Responsibilities will include:

  • Development of verification plan and architecture definition.
  • Development and modifications of new and existing UVM environments
  • Functional coverage closure
  • Management and debugging of regressions

What knowledge and experience should you have?

  • 7+ years of Functional Verification is required
  • Extensive experience with testbench and automated test case design
  • Strong programming skills (SystemVerilog, C++, Linux OS, VHDL)
  • Extensive knowledge in VHDL and Verilog
  • Extensive Verification knowledge
  • IT Environments like Linux, Clearcase, Git, LSF
  • Knowledge in VIP (Verification IP) design
  • Knowledge in SystemVerilog assertions
  • Comfortable utilizing lean and agile principles and practices, including scrum and Kanban.

What educational background should you have?

  • BS Degree or higher in EE, CS, or CE

Applicants must be legally authorized to work in the U.S. without current or future sponsorship.

 

About Correct Designs
Correct Designs is a team of Design and Verification experts. Since 1999, Correct Designs has provided world class verification consulting and training services to top semiconductor clients nationwide.

In addition to offering our engineers the opportunity to participate in challenging projects with industry-leading teams, we offer unequaled in-house training in advanced verification tools and methodologies. With CDI, you’ll have the opportunity to enhance your skills in areas such as UVM, SystemVerilog, in-depth SystemVerilog Assertions, and Verification Planning.

 

Follow us on LinkedIn: https://www.linkedin.com/company/152008/

Learn more at http://www.correctdesigns.com/careers/

Alternatively, you can apply to this job using your profile on one of the following sites:


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